Hey everyone, sorry for the small delay in getting this status update out. We will still call it the February 3rd status update because I did not have the heart to ask Sabri to redo this gorgeous image. Did you know that Sabri provides a fresh image for every status update? He is responsible for most of the house style and doing such an amazing job at it. Funny in a way that the person responsible for our visuals is one of our least visible team members.
Anyway, January was a month of steady progress. A number of components are coming together nicely and we are getting more and more community involvement.Ict
The component that has (deservedly) received most attention is Ict. Thanks to Lukas and a lot of community feedback there is a pretty stable code base now, and the number of Ict nodes has grown to over 400. There have been questions what exactly the purpose of Ict is, and rather than formulating my own answer I will give you this great description provided by one of our community members, lambtho:IXI
On the IXI front Samuel has delivered a first version of graph.IXI, which is one of the components that is needed to get the final Qubic implementation working. It will allow a transaction bundle to refer to an arbitrary number of data pieces instead of only being limited to the usual two transactions.
Last week Samuel also started on another important component that is necessary to properly implement Qubic, the timestamping.IXI. This IXI module will be used to determine timestamps on the Tangle with high confidence level and will be based on this paper by our own Serguei Popov.FPGA
On the FPGA/ASIC implementation of the Qubic Computation Model, Donald and Eric worked together to have the Qupla interpreter finally emit Verilog source code that can be compiled by the Verilog tools without any manual changes, which is a milestone that removes a lot of manual labor after each new iteration of code generation. Donald is no...